This invention relates to First-In-First-Out (FIFO) memory devices, and more particularly to FIFO memory devices that interface a port to a data receiving device.
First-In-First-Out (FIFO) memory devices are widely used to store data. FIFO memory devices generally include one or more FIFO memory blocks. In a FIFO memory block, data generally is stored in sequential order as data is written into the memory block. The FIFO memory block typically is sequentially read in the same order as it was written. Thus, the data that is first written into the FIFO device is also the data that is first read from the FIFO device.
FIFO memory devices are widely used to buffer data in network applications. In network applications, data packets may be stored in the FIFO memory device in the sequential order that they are written. For routing or distribution, the data is sequentially read starting from the first data that was written.
A FIFO memory block may be used in a FIFO memory device that interfaces a port to a data receiving device. One important application of FIFO memory devices is under a specification known as the Universal Test and Operation Physical (PHY) Interface for Asynchronous Transfer Mode (ATM) specification or the UTOPIA specification. The UTOPIA specification defines an interface between one or more ports and an ATM device. In this application, the FIFO memory device synchronizes input and output of data between relatively slow physical devices and a relatively high speed ATM device.
For example, an integrated circuit FIFO memory device is marketed by Integrated Device Technology, Inc., the assignee of the present application, as Device IDT77105. See the Data Sheet entitled xe2x80x9cPHY (TC-PMD) for 25.6 and 51.2 Mbps ATM Networksxe2x80x9d, IDT77105, December 1998. The IDT77105 supports Asynchronous Transfer Mode (ATM) data communications and networking. The IDT77105 provides the Transmission Convergence (TC) and Physical Media Dependent (PMD) layers of a 25.6 or 51.2 Mbps physical interface suitable for ATM networks using Unshielded Twisted Pair (UTP) Category 3 (or better) wiring.
FIG. 1 is a block diagram of a conventional FIFO memory device, such as the one used in the IDT77105. As shown in FIG. 1, the FIFO memory device 100 includes a data input interface 102 that is coupled to an input port 106, such as a serial port. A data output interface 104 is coupled to a data receiving device 108, such as an ATM device. A FIFO memory block 110 is also provided. The data input interface 102 and the data output interface 104 generally operate at different clock speeds and generally operate asynchronously from one another.
Still continuing with the description of FIG. 1, the data input interface 102 includes a clock recovery circuit 112 that recovers a clock from a serial data signal, to generate a data signal 114 and a recovered clock 116. A cell assembly circuit 118 assembles the data into cells and writes the cells into the FIFO 110 one byte at a time. For example, under the UTOPIA specification, cells having 53 bytes of data may be assembled. The cell assembly circuit writes data into the FIFO 110. In FIG. 1, the FIFO 110 can hold three cells C1-C3, although in general, the FIFO may be configured to hold fewer or more cells. A first counter 122 counts the number of cells that are in the FIFO 110 under control of a first controller 124. More specifically, when a cell is written into the FIFO 110, the first controller provides an enable signal to the UP input of the first counter 122, so that the first counter 122 increments the count. The count is also fed back to the first controller 124.
The data output interface 104 includes a parallel output interface 130 that is responsive to data that is read from the FIFO 110 provide the data that is read from the FIFO 110 to the data receiving device 108. A second counter 132 is provided to count the number of cells that are in the FIFO 110. The second counter 132 is controlled by a second controller 134. When a cell is read from the FIFO 110, the second controller 134 provides an enable signal to the down (DN) input of the second counter 132 to decrement the count. The count is also fed back to the second controller 134. The parallel output interface 130, the second counter 132 and the second controller 134 are synchronized by a data output interface clock 136 that may be provided from external of the FIFO memory device 100. As shown in FIG. 1, the data output interface clock 136 is independent of the recovered clock 116.
Since the data input interface 102 and the data output interface 104 operate asynchronously, it is desirable to synchronize the first counter 122 and the second counter 132, so that each counter accurately reflects the number of cells in the FIFO 110, notwithstanding the different clock frequencies of the data input interface recovered clock 116 and the data output interface clock 136. In order to provide this synchronization, a first pulse generator 150 is provided in the data input interface 102, and a second pulse generator 160 is provided in the data output interface 104. Upon incrementing the first counter 122, the first controller 124 also enables the first pulse generator 150 to generate a pulse that is provided to the UP input of the second counter 132. Thus, the second counter increments its count in response to the first pulse 152 from the first pulse generator 150. Similarly, upon enabling the second counter 132 for decrementing by the second controller 134, the second controller also enables the second pulse generator 160 to provide a second pulse 162 to the down (DN) input of the first counter 122. Thus, when a cell is written into the FIFO 110, the first pulse generator 150 causes the second counter 132 to increment. When a cell is read from the FIFO 110, the second pulse generator 160 causes the first counter 122 to decrement.
Since the data input interface 102 and the data output interface 104 operate at different clock frequencies, and may be selectively enabled and disabled by the respective input port 106 and the data receiving device 108, it is desirable to ensure that the first and second counters 122 and 132 are able to respond to the second pulse 162 and first pulse 152 respectively, so that an accurate count is maintained. In order to ensure that the first and second counters can respond to the pulses, a multiple cycle pulse is generally provided by the first pulse generator 150 and the second pulse generator 160, so that the respective second counter 132 and first counter 122 can sample the pulses, and thereby increment or decrement the counter.
Unfortunately, the need to ensure that the pulses are sampled may place operating constraints on the clock frequency of the data input interface 102 and/or the data output interface 104. The need to provide a multiple cycle pulse may also reduce the overall operational speed of the FIFO memory device 100. Moreover, notwithstanding the provision of wide pulses, it may not be ensured that the first or second counter 122 or 124 will be active during the pulse interval. Inaccurate counts may therefore be produced.
These problems are illustrated in FIG. 2 which is a timing diagram of operations of a FIFO memory device 100 of FIG. 1. As shown in FIG. 2, the recovered clock 116 may have a predetermined frequency. The first pulse is output in synchronism with the recovered clock 116. In order to ensure that the second counter 132 can sample the first pulse 152, a constraint may need to be placed on the clock frequency of the data output interface clock 136, so that it is sufficiently high frequency to ensure that the first pulse 152 is sampled. Moreover, since the data output interface 104 may be placed in an inactive mode by the data receiving device 108, it may not be ensured that the first pulse 152 will be detected, notwithstanding constraints that are placed on the clock frequency. Similar considerations apply to the second pulse 162 and the first counter 122.
It is therefore an object of the present invention to provide improved FIFO memory devices and methods for interfacing a port to a data receiving device.
It is another object of the present invention to provide FIFO memory devices and methods that can ensure accurate counts of cells that are written in and read from the FIFO memory, notwithstanding the asynchronous operation of the data input interface and the data output interface thereof.
It is yet another object of the present invention to provide FIFO memory devices and methods that need not constrain the clock frequencies of a data input interface and a data output interface that operate asynchronously.
It is still another object of the present invention to provide FIFO memory devices and methods that can provide accurate counts of cells written into and read from a FIFO memory, notwithstanding that the data input interface and/or the data output interface are inactive.
These and other objects are provided, according to the present invention, by a FIFO memory device that includes a FIFO memory block, a data input interface that writes data into the FIFO memory block in synchronization with a first clock, and a data output interface that reads the data from the FIFO memory block in synchronization with a second clock. The data input interface provides a first indication to the data output interface that the received data has been written into the FIFO memory block. The first indication persists until reset by the data output interface. The data output interface provides a second indication to the data input interface that the received data has been read from the FIFO memory block. The second indication persists until reset by the data input interface.
By providing the first and second indications between the data input interface and the data output interface that persist until reset, the first and second data interfaces may always be aware that a cell has been written into or read from the FIFO. Thus, timing constraints need not be placed between the first and second clocks in order to ensure that an accurate count of cells in the FIFO is maintained by the data input interface and the data output interface. Moreover, the first and second indications persist notwithstanding the deactivation of the data input interface and/or the data output interface. Thus, upon reactivation, an accurate count of cells in the FIFO may be obtained.
More specifically, FIFO memory devices according to the invention interface a port to a data receiving device. The FIFO memory devices include a FIFO memory block. A data input interface is coupled to the port and to the FIFO memory block. The data input interface receives data from the port, assembles the received data into cells, and writes the cells into the FIFO memory block. A data input interface includes a first counter that counts the number of cells that are written into the FIFO memory block. The data output interface is coupled to the FIFO and to the data receiving device. The data output interface reads the cells from the FIFO memory block and provides the cells to the data receiving device. The data output interface includes a second counter that counts the number of cells that are read from the FIFO memory block.
A first register is coupled between the data input interface and the second counter, to store therein a first indication that a cell has been written into the FIFO memory block. The second counter is responsive to the first indication to increment the number of cells that are written into the FIFO memory block. A second register is coupled between the data output interface and the first counter, to store therein a second indication that a cell has been read from the FIFO memory block. The first counter is responsive to the second indication to decrement the number of cells that are read from the FIFO memory block.
In a first embodiment of the present invention, the first register comprises a first latch including a first set input, a first clear input and a first output. The first set input is coupled to the data input interface. The first clear input is coupled to the data output interface and the first output is coupled to the second counter. The second register comprises a second latch including a second set input, a second clear input and a second output. The second set input is coupled to the data output interface. The second clear input is coupled to the data input interface and the second output is coupled to the first counter.
In another embodiment of the present invention, the first register comprises a third counter including a first increment input, a first clear input and a first output. The first increment input is coupled to the data input interface. The first clear input is coupled to the data output interface and the first output is coupled to the second counter. The second register comprises a fourth counter including a second increment input, a second clear input and a second output. The second increment input is coupled to the data output interface. The second clear input is coupled to the data input interface and the second output is coupled to the first counter. Accordingly, the first and second registers, whether embodied as latches, counters or other storing means, provide a count of cells in the FIFO from the data input interface to the data output interface and from the data output interface to the data input interface that persist until reset by the data output interface and the data input interface respectively. Thus, the need to tailor the clock frequencies to ensure sampling of pulses may be eliminated, and an accurate count may be obtained notwithstanding that the data input interface and/or the data output interface may be inactive.
In a preferred embodiment of the present invention, the data input interface includes a clock recovery circuit that is responsive to the port, to recover a clock from the data that is received at the port. A cell assembly unit is responsive to the clock recovery unit and is coupled to the FIFO memory block, to assemble the received data into cells and to write the cells into the FIFO memory block. A controller is responsive to the clock recovery circuit and/or to the cell assembly circuit, to increment the first counter and to provide the first indication to the first register upon storing a cell in the FIFO memory block. The port may be a serial port, and the data receiving device may be an ATM device. It will also be understood that the counters and registers may be responsive to bits, bytes, groups of bits and/or groups of bytes that are written into or read from the FIFO memory block, rather than being responsive to cells of 53 or other predetermined numbers of bytes.
Methods of interfacing a port to a data receiving device using a FIFO memory and first and second counters according to the invention include the steps of receiving data from the port, assembling the received data into cells, writing the cells into the memory, reading the cells from the FIFO memory and providing the read cells from the FIFO memory to the data receiving device. A first indication that a cell has been written into the FIFO memory is stored. The second counter is incremented in response to the step of storing a first indication. A second indication that a cell has been read from the FIFO memory is also stored and the first counter is decremented in response to the step of storing the second indication. Accordingly, the performance and/or accuracy of FIFO memory devices may be improved.